Enhanced SRAM Design through Recovery Boosting

Abstract

SRAM based structures are there within
microprocessor architecture. Important lifetime reliability problem in
microprocessors is Negative Bias Temperature Instability (NBTI). As
one of the pMOS device in the memory cell always has an input
„0‟,SRAM arrays are susceptible to NBTI. An existing recovery
technique for SRAM cell aims to balance the degradation of two
pMOS device by attempting to keep their inputs at logic „0‟, exactly
50% of the time. But the problem with this technique is that, one of the
devices is always in the negative bias condition at any given time.
So we propose a new technique called Recovery Boosting. By
slightly modifying the conventional SRAM cell, we put both pMOS
device in the memory cell to the recovery mode. Recovery Boosting
provides reduction in NBTI and significant improvement in the static
noise margin of the issue queue with reduction in power consumption.
The tool used for simulation is MICROWIND and digital schematic
editor and simulator.