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A Comparative Analysis of Low Power D Flip Flop Using Leakage Power Reduction Techniques

S. Ranjith, N. Mathan, D. Irudaya Praveen, T. Ravi


This paper proposes a new topology to low power approaches for very large scale integration (VLSI) design. Power dissipation is one of the major concerns when designing a VLSI system. Until recently, dynamic power was the only concern. However, as the technology feature size shrinks, static power, which was negligible before, becomes an issue as important as dynamic power. Since static power increases dramatically in nanoscale silicon VLSI technology, the importance of reducing leakage. This paper describes a low-leakage technique. We are doing comparable analysis of different low power, leakage current reduction techniques like SLEEP approach, STACK, SLEEPY–STACK, SLEEPY KEEPER, SLEEPY–STACK with KEEPER, LEAKAGE FEEDBACK and LEAKAGE FEEDBACK with STACK techniques. Which reduces leakage power while saving exact logic state. Based on simulation results a conventional D Flip flop with the Full sleep approach achieves up to 95 % less power consumption.


Conventional D Flip Flop, Low Power Dissipation Techniques, Circuit Simulation.

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Pankaj Kr. Pal, Rituraj S. Rathore, AshwaniK.Rana, GauravSaini“New Low-Power Techniques: Leakage Feedback with Stack & Sleep Stack with Keeper” Int‟l Conf. on Computer & Communication Technology | ICCCT‟10 | IEEE- 978-1-4244-9034-/10 2010

ParamitaChowdhury and Amitava Das, “The Silent Transistor: A New Topology for LowPower Memory Cell” Proc. of Int. Conf. on Control, Communication and Power Engineering 2010,

AGARWAL, A., HAI, L., and ROY, K., “DRG-Cache: A Data Retention Gated- Ground Cache for Low Power,” Proceedings of the Design Automation Conference, pp. 473 – 478, June 2002.

AGARWAL, A., ROY, K., and VIJAYKUMAR, T. N., “Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology,” Proceedings of the Design, Automation and Test in Europe, pp. 778–783, March 2003.

AZIZI, N., MOSHOVOS, A., and NAJM, F., “Low-Leakage Asymmetric-Cell SRAM,” Proceedings of the International Symposium on Low Power Electronics and design, pp. 48–51, August 2002.

International Technology Roadmap for Semiconductors by Semiconductor Industry Association,, 2007.

S. Mutoh et al., “1-V Power Supply High-speed Digital Circuit Technology with Multi-threshold-Voltage CMOS,” IEEE Journal of Solis-State Circuits, Vol. 30, No. 8, pp. 847-854, August 1995.

M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijay kumar, “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep submicron Cache Memories,” International Symposium on LowPower Electronics and Design, pp. 90-95, July 2000.

J.C. Park, V. J. Mooney III and P.Pfeiffenberger, “Sleepy Stack Reduction of Leakage Power,” Proceeding of the International Workshop on Power and Timing Modelling, Optimization and Simulation, pp. 148-158, September 2004.

J. Park, “Sleepy Stack: a New Approach to Low Power VLSI and Memory,” Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. [Online].Available

G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C.Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-kdielectrics reliability issues,” IEEE Transactions on Device and materials Reliability, Vol. 5, Issue 1, pp. 5-19, March 2005.

K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy Caches: Simple Techniques for Reducing Leakage Power,”Proceedings of the International Symposium on Computer Architecture, pp. 148-157, May 2002

Kim, N., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., And Narayanan, V., “Leakage Current: Moore‟s Law Meets Static Power,” Ieee Computer, Vol. 36, Pp. 68–75, December 2003

Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu., “New paradigm of predictive MOSFET and interconnect modelling for early circuit design,” Proceeding of IEEE Custom Integrated Circuits Conference, pp. 201-204, June 2000.

K.-S. Min, H. Kawaguchi and T. Sakurai, “Zigzag Super Cut-offCMOS (ZSCCMOS) Block Activation with Self-Adaptive VoltageLevel Controller: An Alternative to Clock-gating Scheme in LeakageDominant Era,” IEEE International Solid-State Circuits Conference,pp. 400-401, February 2003.

Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modelling of Transistor Stacks,” International Symposium on Low Power Electronics and Design, pp. 239-244, August 1998.

USAMI, K. and HOROWITZ, M., “Clustered Voltage Scaling Technique for Low-Power Design,” Proceedings of the International Symposium on Low Power Electronicsand Design, pp. 3–8, April 1995.

USAMI, K., IGARASHI, M., MINAMI, F., ISHIKAWA, T., KANZAWA, M., ICHIDA,M., and NOGAMI, K., “Automated Low-Power Technique Exploiting Multiple SupplyVoltages Applies to a Media Processor,” IEEE Journal of Solid-State Circuits,vol. 33, no. 3, pp. 463–472, March 1998.

A. Kahng, S. Muddu, P. Sharma, “Defocus-aware leakageestimationand control,” International Symposium on Low PowerElectronicsand Design, pp. 263-268, Aug. 2005.

Berkeley Predictive Technology Model,

J. Kao and A. Chandrakasan, "MTCMOS sequential circuits,"Proceedings of European Solid-State Circuits Conference, pp 332-335, September 2001.

ISHIBASHI, K., KOMIYAJI, K., TOYOSHIMA, H., MINAMI, M., OOKI, N., ISHIDA,H., YAMANAKA, T., NAGANO, F., and NISHIDA, T., “A 300 MHz 4-Mb WavepipelineCMOS SRAM Using a Multi-Phase PLL,” IEEE International Solid-StateCircuits Conference, pp. 308–309, February 1995.

JOHNSON, M. C. and ROY, K., “Datapath Scheduling with Multiple Supply Voltagesand Level Converters,” ACM Transactions on Design Automation of ElectronicSystems, vol. 2, no. 3, pp. 227–248, July 1997.

AMRUTUR, B. S. and HOROWITZ, M. A., “Fast Low-Power Decoders for RAMs,”IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1506–1515, October 2001.

AZIZI, N., MOSHOVOS, A., and NAJM, F., “Low-Leakage symmetric-CellSRAM,” Proceedings of the International Symposium on Low Power Electronics andDesign, pp. 48–51, August 2002.



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