A Low Area Overhead Packet-Switched Network On Chip Using MANET

Abstract

Crossbar architectures for packet network switches have become very popular in the networking industry. Crossbar switches are used to route and switch data through a packet network. Their speed and performance are of significant importance. The increasing complexity of integrated circuits drives the research of new intra-chip interconnection architectures. To solve this problem together with the bottleneck problem of arbitration based buses, a novel approach in network-on-a-chip interconnect has been investigated. A network-on-chip adapts concepts originated in the distributed systems and computer networks subject areas to connect IP cores in a structured and scalable way, pursuing the goal of achieving superior bandwidth to conventional intra-chip bus architectures. This paper presents the design of a switch targeted to a mesh interconnection topology. Each switch has 5 bi-directional ports, connecting 4 neighbor switches and a local IP core. They employ a XY routing algorithm, with input queue buffers. The main objective is to develop a switch with a small area, enabling its immediate practical use. The switch and a 2x2 mesh network is simulated through VERILOG.