Video Surveillance System using FPGA
In advance media encoding the proposed project
(video surveillance system) gives the observation from a distance to prevent/investigate criminal activity. The proposed project is an alldigital platform for real-time video/image acquisition, scheduling, processing, and display. The Xilinx FPGA vertex allows jump tostarting high-performance imaging, and video processing designs.The heart of the proposed project is four cameras, two highly programmable Xilinx FPGA Vertex ICs, video decoder, video encoder, and a wide range of video interfaces. The four cameras are scheduled by using mux tree based round robin scheduler which is
programmed in one of the Vertex IC. The decoded data from video decoder is given to one of the FPGA vertex ICs and processed on it. The processed data is given to video encoder from FPGA. The flexibility of the proposed project architecture makes it suitable as a development platform for a variety of imaging, video, and
E. Shin et al., “Round-robin arbiter design and generation,” in Proc.
IEEE Int. Symp. Syst. Synthesis, Oct. 2002, pp. 243–248.
Kangmin Lee, Se-Joong Lee, and Hoi-Jun Yoo, “Low Power Networkon-
Chip for High-Performance Soc Design,” IEEE Tran. VLSI, Vol.14,
no.2, Feb. 2006.
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