High Performance Partial Product Binary to Decimal (PPBD) Converter based Multiplier

Abstract

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. Multipliers are vital components of any processor or computing machine. Hence better multiplier architectures are bound to increase the efficiency of the system. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. Throughput is the measure of how many multiplications can be performed in a given period of time. Two most common multiplication algorithms followed in the digital hardware are array multiplication algorithm and Booth multiplication algorithm. High Performance Partial Product Binary to Decimal (PPBD) Converter based Multiplier is one such promising solution. The designing can done using VERILOG and simulated, synthesized using Questa-sim.