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CMOS Full-Adders for Arithmetic Applications in DSP

K. Saranya, R. Saran Kumar


We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure. Two proposed logic of DPL(dual pass transistor logic) and SR-CPL(swing restored CPL)is used. The proposed full adder which has low power and delay is used for two tab FIR filter in DSP applications. The partial product of multiplier in FIR can be replaced using the full adder which reduces delay in the computation of the partial products. Low Power analysis of full adder is done using 0.125um technology S-Edit Tanner EDA tool and simulation is done using Xilinx. The delay of the FIR filter using full adder is found to be less than the conventional FIR filter. This full adder can also be used in ALU operation which contains many arithmetic and logic units. This full adder reduces the delay when used in the operation.


Full-Adder, High-Speed, Low-Power.

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