Efficient Clock Power Reduction using Merging Flip-Flop Technique in LFSR

M. Kowsalya, C. Pandiarajan


Power has become a bottleneck for circuit implementation. In integrated circuits, power consumption is one of the top three challenges. Due to the massive increase of portable electronic device there is a need of low power flip flops in low power circuits. Clock power is the major dynamic power source. Our algorithms are very effective in reducing flip-flop clock power consumption. Several flip-flops can share a common clock buffer to avoid unnecessary power waste. Besides power reduction, the objective of minimizing the total wire length also is considered to the cost function. In this work the objective of minimizing power reduction and wire length reduction is extended for sequential circuits linear feedback shift register (LFSR). The flip-flop replacement without timing and placement capacity constraints violation becomes a quite difficult problem. To deal with the complexity competently this paper proposed several techniques. By using this method we can achieve 33% of overall power reduction. 23% of clock power reduction.


LFSR, Flip-Flops, Low Power Consumption, Merging Flip Flop, Reasonable Process Time.


Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, and Soon-Jyh Chang Member IEEE “Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops”, IEEE transactions on very large scale integration (vlsi) systems, This article has been accepted for inclusion in a future issue of this journal.

C. Bron and J. Kerbosch, “Algorithm 457: Finding all cliques of an undirected graph,” ACM Commun., vol. 16, no. 9, pp. 575–577, 1973.

Y. Cheon, P.-H. Ho, A. B. Kahng, S. Reda, and Q. Wang, “Power-aware placement,” in Proc. Design Autom. Conf., Jun. 2005, pp. 795–800.

Y.-T. Chang, C.-C. Hsu, P.-H. Lin, Y.-W. Tsai, and S.-F. Chen, “Post-placement power optimization with multi-bit flip-flops,” in Proc. IEEE/ACM Comput.-Aided Design Int. Conf., San Jose, CA, Nov. 2010,pp. 218–224.

D. Duarte, V. Narayanan, and M. J. Irwin, “Impact of technology scaling in the clock power,” in Proc. IEEE VLSI Compute. Soc. Annu. Symp., Pittsburgh, PA, Apr. 2002, pp. 52–57.

P. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R.L.Allmon,“High-performance microprocessor design,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 676–686, May 1998.

W. Hou, D. Liu, and P.-H. Ho, “Automatic register banking for low power clock trees,” in Proc. Quality Electron. Design, San Jose, CA, Mar. 2009, pp. 647–652.

H. Kawagachi and T. Sakurai, “A reduced clock-swing flip-flop (RCSFF) for 63% clock power reduction” in VLSI Circuits Dig. Tech. Papers Symp., Jun. 1997, pp. 97–98.

Faraday Technology Corporation [Online]. Available: http://www. faraday-tech.com/index.htm

CAD Contest of Taiwan [Online]. Available: http://cad_contest.cs.nctu.edu.tw/cad11


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.