Fault Tolerant Secured System Using Efficient ML Decoder/Detector

Abstract

To prevent soft errors from causing data corruption, memories are typically protected with error correction codes. An advanced error correction codes are used when an additional protection is needed. The majority logic decoder/detector codes are used for memory application because of correcting large number of soft errors, less decoding time, area consumption. The EG-LDPC codes are suitable for error correction using majority logic decoder/detector. Because the EG-LDPC codes are small, powerful and easily implemented in terms of decoding latency and complexity and this design achieving very high data rate while minimizing complexity. The proposed improved majority logic decoder/detector to perform silent data error detection in simple way using additional error detection technique and also reducing the area of the majority gate using sorting network. Hence the decoding process uses less number of cycles, reduces the area and also reducing the power consumption.