Open Access Open Access  Restricted Access Subscription or Fee Access

An FSM Based Memory Architecture to Valuate Memory Fault for OFDM

R. Cauvery, B. Muthupandian, Dr.R. Ganesan

Abstract


Todays emerging technology is to integrate the electronic device which arises memory fault in system and also occupy more space. Here, proposed that Finite state machine based soft memory repair strategy to reduced access time, lesser occupancy of circuit board and lower power consumption. Linear-Density Parity-Check (LDPC) decoder was used in architecture to provide acceptable error tolerance, and implement of an orthogonal frequency-division multiplexing (OFDM) system as measured by the Bit Error Rate (BER) and the Packet Error Rate (PER). The proposed memory strategy was improved at 0.52 dB gain .

Keywords


Interleaver, Orthogonal Frequency-Division Multiplexing Receiver, Finite State Machine, Soft Memory Repair, System-On-Chip.

Full Text:

PDF

References


S.-K. Lu, C.-L. Yang, Y.-C. Hsiao, and C.-W. Wu, “Efficient BISR techniques for embedded memories considering cluster faults,” IEEE Trans. conf, Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 184–193, Feb. 2010.

Jayarani, M.A., Jagadeeswari, M.” A novel fault detection and correction technique for memory applications” Computer Communication and Informatics (ICCCI), 2013 International Conference on 4-6 Jan. 2013

Y.-L. Ueng, Y.-L. Wang, L.-S. Kan, C.-J. Yang and C.-J. Chen,“Jointly designed architecture-aware LDPC convolutional codes and memory-based shuffled decoder architecture,” IEEE Trans. Signal Process., vol. 60, no. 8, pp. 4387–4402, Aug. 2012.

Y.-L. Ueng, Y.-L. Wang, L.-S. Kan, C.-J. Yang, and C.-J. Chen,“An efficient multi-standard LDPC decoder design using hard-ware-friendly shuffled decoding,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 3, pp. 743–756, Mar 2013.

S. K. Thakur, R. A. Parekhji, and A. N. Chandorkar, “On-chip test and repair of memories for static and dynamic faults,” in Proc. Int. Test Conf., 2012, pp. 1–10.

M. Ottavi, L. Schiano, X. Wang, Y.-B. Kim, F. J. Meyer, and F. Lombardi,“Evaluating the yield of repairable SRAMs for ATE,” IEEE Trans.conf, Instrum. Meas., vol. 55, no. 5, pp. 1704–1712, Oct. 2009.

J. L. Ramsey, “Realization of optimum interleavers,” IEEE Trans.conf, Inf. Theory, vol. 16, no. 3, pp. 338–345, May 2012.

S.M.Al-Harbi and S. K. Gupta, “An efficient methodology for generat- ing optimal and uniform march tests,” in Proc. VLSI Test Symp., 2012.

D. Forney, “Burst-correcting codes for the classic bursty channel,” IEEE Trans.conf, Commun. Technol., vol. 19, no. 5, pp. 772–781, Oct. 2009.

R. Dekker, F. Beenker, “Fault modeling and test algorithm development for static random access memories,” in Proc. IEEE Int. Test Conf., Sep 2012.

S.-K. Lu and C.-H. Hsu, “Fault tolerance techniques for high capacity RAM,” IEEE Trans.conf, Rel., vol. 55, no. 2, pp. 293–306, Jun. 2011.

Optimal Training Signals for MIMO OFDM Channel Estimation Hlaing Minn, Member, IEEE conf and Naofal Al-Dhahir

OFDM for Optical Communications Jean Armstrong, Senior Member, IEEE 2011.

R. Dekker, F. Beenker, and L. Thijssen, “Fault modeling and test Algorithm development for static random access memories,” in Proc. IEEE Int. Test Conf., Sep. 2010, pp. 343–352.

Optimal Training Signals for MIMO OFDM Channel Estimation Hlaing Minn, Member, IEEE conf and Naofal Al-Dhahir.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.