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Power Supply Noise Reduction in Mixed Signal System-On-Chip with Active Decoupling Inductor

S. Seenuvasamurthi, G. Nagarajan


When integrating analog and digital circuits onto a mixed-mode chip, power supply noise is a major limitation on the performance of the analog circuitry. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates. This paper introduces an active inductor implementation and analyze the various characteristics of the active inductor in the practical scenario. The proposed CMOS active inductor exhibits better power supply noise rejection of 30 dB when the inverter circuit is used as the load. The proposed CMOS active inductor circuit is implemented in GPDK 180nm CMOS technology. Also the simulation result shows that the noise measured is only 5.788 μV with active inductor whereas the noise measured without active inductor is 50 mV.


CMOS Active Inductor, Deep Sub-Micron, Power Supply Noise, Technology Scaling.

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