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Power Supply Noise Reduction Circuit for Mixed Signal VLSI Systems
Abstract
Noise is a significant factor in the analog and digital circuits which determine the characteristics of the system. The speed at which a digital gate switches depends on the clock frequency. A digital system is made up of large a number of digital gates. When the clock frequency is high and several gates switch simultaneously, the surge current will be high. The surge current loads the power supply, causing power supply noise. The primary cause of power supply noise is the parasitic resistance and inductance associated with power rails of the integrated circuit. The peak current causes considerable voltage drop across the parasitic resistance and inductance, leading to reduction in the power supply available to the system. In most cases the peak power supply noise is the root cause of the system failure. So it is inefficient to monitor the signature of transient power supply noise. Methods are proposed to find the peak value of power supply noise using withholding circuits and monitor the corresponding signature. In this work, a power supply stabilization circuit with negative feedback is proposed and utilized for power supply stabilization. The noise voltage is -52.04 dBVrms observed at 100 KHz and it is considerably very less when compared with the existing technique with noise voltage of -24.47 dBVrms. The proposed method can be easily being combined with other existing methods to further reduce the noise.
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References
Ajay Taparia, Bhaskar Banerjee and T. R. Viswanathan, "Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems", IEEE Trans. VLSI systems, vol. 19, no. 11, pp. 1960-1968, Nov. 2011.
S. Kiaei, D. J. Allstot, K. Hansen and N. K. Verghese, “Noise considerations for mixed-signal RF IC transceivers,” ACM J. Wireless Netw., vol. 4, pp. 41–53, Jan. 1998.
D. Leenaerts and P. de Vreede, “Influence of substrate noise on RF performance,” in Proc. Eur. Solid-State Circuits Conf., pp. 300–304, Sep. 2000.
S. Donnay and G. Gielen, Eds., “Substrate Noise Coupling in Mixed Signal ICs”, Dordrecht, The Netherlands: Kluwer, 2003.
A. Afzali-Kusha, M. Nagata, N. K. Verghese and D. J. Allstot, “Substrate noise coupling in SoC design: Modeling, avoidance and validation,” Proc. IEEE, vol. 94, no. 12, pp. 2109–2138, Dec. 2006.
K. Iniewski, Wireless Technologies: “Circuits, Systems and Devices”, Boca Raton, FL: CRC, ch. 20, 2008.
S. Zhao, K. Roy and C.K. Koh, “Decoupling capacitance allocation and its application to power-supply noise-aware floor planning,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 1, pp. 81–92, Jan. 2002.
P. Larsson, “Measurements and analysis of PLL jitter caused by digital switching noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1113–1119, Dec. 2001.
M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. G. E. Gielen and H. J. De Man, “Digital ground bounce reduction by supply current shaping and clock frequency modulation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 1, pp. 65–76, Jan. 2005.
H.T. Ng and D. J. Allstot, “CMOS current steering logic for low voltage mixed-signal circuits,” IEEE Trans. Very Large-Scale Integr. (VLSI) Syst., vol. 5, no. 5, pp. 301–308, Sep. 1997.
E. Albuquerque et al., “A new low-noise logic family for mixed-signal integrated circuits,” IEEE Trans. Circuit Syst, I, Fundam. Theory Appl., vol. 46, no. 12, pp. 1498–1500, Dec. 1999.
T. Liu, J. D. Carothers and W. T. Holman, “Active substrate coupling noise reduction method for ICs,” Electron. Lett., vol. 35, p. 1631634, Sep. 1999.
A. Taparia, T. R. Viswanathan and B. Banerjee, “Active inductor for power-supply decoupling in mixed signal systems,” in Proc. IEEE Dallas Circuits Syst. Workshop, pp. 1–4, 2008.
Hailang Wang and Emre Salman, “Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 12, pp. 2983-2991, Dec. 2015.
Yakov Kaplan and Shmuel Wimer, “Mixing Drivers in Clock-Tree for Power Supply Noise Reduction”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 62, no. 5, pp. 1382-1391, May 2015.
Xiaoxiao Wang, Dongrong Zhang, Donglin Su, Leroy Winemberg and Mark Tehranipoor, “A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol.24, no. 5, pp. 1715-1727, May 2016.
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