Embedded Systems Neural Network Stream Processing Core (NnSP)

Abstract

Exploiting neural networks native parallelism and interaction locality, dedicated parallel hardware implementation of neural networks is essential for their effective use in time critical applications. The architecture proposed in this paper is a parallel stream processor called Neural Networks Stream Processor or NnSP which can be programmed to realize different neural-network topologies and architectures. NnSP is a collection of programmable processing engines organized in custom FIFO based cache architecture and busing system. Streams of synaptic data flow through the parallel processing elements, and computations are performed based on the instructions embedded in the preambles of the data streams. The command and configuration words embedded in the preamble of a stream, program each processing element to perform a desired computation on the upcoming data. The packetized nature of the stream architecture brings up a high degree of flexibility and scalability for NnSP. The stream processor is synthesized targeting an ASIC standard cell library for SoC implementation and also is realized on Xilinx VirtexII-Pro SoPC beds. A neural network employed for mobile robot navigation control, is implemented on the realized SoPC hardware. The realization speedup achievements are presented here.