Design and Implementation of Low Power Delay and Area Efficient Carry Select Adder

Abstract

Carry Select Adder is known to be the fastest adder among the conventional adder structure. Due to rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has been developed by identifying the redundant logic operation and data dependence of the Conventional Carry Select Adder and Binary To Excess One Converter .In the proposed CSLA scheme the redundant logic operations present in the conventional CSLA are eliminated. Carry Selection operation is scheduled before the calculation of the final sum. Bit pattern of two anticipating Carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of Carry Select and generation unit. An efficient CSLA design is obtained using optimized logic unit. The proposed Carry Select Adder scheme is designed and implemented in cadence RC Encounter 180nm technology. Synthesis result shows that the proposed CSLA design involves 53% less area and consumes 50% less energy than Conventional CSLA and also the proposed CSLA design involves 20% less area and consumes 37% less energy than the BEC based CSLA  on average, for different bit-widths.