Open Access Open Access  Restricted Access Subscription or Fee Access

Optimization of Area in Digit Serial Multiple Constant Multiplication at Gate Level

N. Logeshwari, B. Aarthi, K. Manikandan, K. Yogeswari, M. Vishnupriya, S. Priya

Abstract


In the last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel multiple constant multiplications (MCM) operation which increases the complexity of many digital signal processing systems. Multiple constant multiplications (MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low complexity MCM operations. In this paper, we address the problem of optimizing the gate-level area in digit-serial MCM designs.

Keywords


0–1 Integer Linear Programming (ILP), Digit-Serial Arithmetic, Finite Impulse Response (FIR) Filters, Gate-Level Area Optimization, Multiple Constant Multiplications

Full Text:

PDF

References


L. Aksoy, E. Costa, P. Flores, and J. Monteiro, “Optimization of area in digital FIR filters using gate-level metrics,” in Proc. DAC, 2007.

I.-C. Park and H.-J. Kang, “Digital filter synthesis based on minimal signed digit representation,” in Proc. DAC, 2001, pp. 468–473.

A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,”

R. Hartley and P. Corbett, “Digit-serial processing techniques,” Jun. 1990.

P. Flores, J. Monteiro, and E. Costa, “An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications,” in Proc. Int. Conf. Comput.-Aided Design, Nov. 2005.

J. McClellan, T. Parks, and L. Rabiner, “A computer program for designing optimum FIR linear phase digital filters,” Dec. 1973.

H. Nguyen and A. Chatterjee, “Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis,” Aug. 2000

K. Johansson, O. Gustafsson, A. Dempster, and L. Wanhammar, “Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic,” May 2004.

Y.-N. Chang, J. Satyanarayana, and K. Parhi, “Low-power digit-serial multipliers,”1997.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.