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SOC Implementation of Universal CORDIC Processor Based MFCC for Isolated Digit Recognition System on a Soft- Core Processor

Dr.V. Amudha

Abstract


In this paper an universal Coordinate Rotation DIgital Computer (CORDIC) processor was used for the implementation of Mel Frequency Cepstral Coefficient (MFCC). MFCC involves DFT, inverse FFT, logarithm and square root operations. All these trigonometric functions involve iterative operations on different samples. CORDIC algorithm allows a unified approach to implement the trigonometric functions either in rotation or in vector mode operations. Fully hardware implementation of the whole process may involve more resources also more data path control. Hence, this implementation approaches Hardware/Software co-design techniques on NiosII soft-core processor. Hidden Markov Model (HMM) is employed as a classifier, the recognition phase involves Viterbi decoder, is implemented as custom hardware and yields „772‟ times higher speed than the high level programming(C++) on the System on Programmable chip(SOPC) platform. MFCC implementation on Nios-II soft-core processor yields a speed improvement of “10” times compared to the high level programming.

Keywords


Hardware/Software Co-Design, Soft-Core, Custom Hardware, HMM, LPC and MFCC.

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References


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