Energy Efficient 3-Transistor XOR-XNOR for Arithmetic Applications
Abstract
We present two high-speed and low-power full-adder
cells designed with an alternative internal logic structure and
pass-transistor logic styles that lead to have a reduced power-delay product (PDP).We carried out a comparison against other full adders reported as having low power-delay product, power consumption and area. All the full adders were designed with a 0.18μm CMOS technology, and were tested using a comprehensive test bench that allowed to measuring the current taken from the full adder inputs besides the current provided from the power supply. In proposed work we are using full adders with 3-transistor XOR-XNOR.It is used for
further power consumption.
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Marino Aguirre and Monico Linares-Aranda, ―CMOS full adders for
energy efficient arithmetic applications‖ IEEE Trans. VLSI systems, vol.
, no. 4, April 2011.
A.M.Shams, ―Performance evaluation of one bit CMOS adder cells,‖
IEEE Trans. Electronic Computers, vol. 13, no. 1, pp. 14-17, Feb 1964.
E. Bloch, ―Principles of CMOS VLSI Design,‖ Proc. Eastern Joint IREAIEE-
ACM Computer Conf., no. 16, pp. 48-58, 1959.
L. Dadda, ―A comparison of CMOS circuit techniques: Differential
cascode voltage switch logic versus conventional logic,‖Alta Frequenza,
vol. 34, pp. 349-356, 1965.
B. Parha. ―A 3.8 ns CMOS 16�16-b multiplier using complementary
pass-transistor logic Oxford Univ. Press, p. 179, 2000.
K.C. Bickerstaff, M.J. Schulte, and E.E. Swartzlander Jr., ―A 1.5 ns 32-b
CMOS ALU in double pass-transistor logic‖, vol. 9, no. 3, pp.181-191,
Apr. 1995.
W.J. Townsend, E.E. Swartzlander Jr and J.A. Abraham,‖ Low-power
logic styles: CMOS versus pass-transistor logic, ‖ Proc. SPIE, Advanced
Signal Processing Algorithms, Architectures, and Implementations XIII,
pp. 552-560, 2003.
S. Waters, ― novel hybrid pass logic with static CMOS output drive
full-adder cell,‖ in Proc. IEEE Int. Symp. Circuits May 2003,pp 302-319.
Mountassar Maamoun, Mehdi Neggazi, Abdelhamid Meraghni, and
Daoud Berkani―A review of 0.18-μmfull adder performances for tree
structured arithmetic circuits,‖ World Academy of Science, Engineering
and Technology 45 2008.
Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu
Yoshihara, and Yasutaka Horiba, , ―Design of robust, energy-efficient full
adders for deep-sub micrometer design using hybrid-CMOS logic style,‖
JSSC,vol.36, no. 2, February 2001.
Robert Montoye, et.al―Energy-efficient high performance circuits for
arithmetic units,‖ ISSCC 2003.
Yuan-Ho Chen, Tsin-Yuan Chang, and Chung-Yi Li, ―ASIC
implementation of 1-bit full adder,‖ IEEE Transactions On Very Large
Scale Integration (VLSI) Systems, Vol. 19, No. 4, April 2011.
Nicola PetraDavideDe Caro Valeria Garofalo, Ettore Napoli, and Antonio
Giuseppe Maria Strollo, ―A new design of the CMOS full adder,‖ IEEE J.
Solid-State Circuits,IEEE Transactions On Circuits And Systems—I:
Regular Papers, Vol. 58, No. 5, May 2011.
Jiun-Ping Wang, Shiann-Rong Kuang, and Shish-Chang Liang, ―An
alternative logic approach to implement high-speed low-power full adder
cells,‖ IEEE Transactions On Very Large Scale Integration (VLSI)
Systems, Vol. 19, No. 1, January 2010
A. Haj, ―Performance analysis of low-power1-bit CMOS full adder
cells,‖International Journal of Applied Science and Engineering, 2003,
-171.
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