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Energy Efficient 3-Transistor XOR-XNOR for Arithmetic Applications

P. Sathya, G.R. Mahendrababu


We present two high-speed and low-power full-adder
cells designed with an alternative internal logic structure and
pass-transistor logic styles that lead to have a reduced power-delay product (PDP).We carried out a comparison against other full adders reported as having low power-delay product, power consumption and area. All the full adders were designed with a 0.18μm CMOS technology, and were tested using a comprehensive test bench that allowed to measuring the current taken from the full adder inputs besides the current provided from the power supply. In proposed work we are using full adders with 3-transistor XOR-XNOR.It is used for
further power consumption.


Arithmetic, Full-Adder, Low-Area, Low-Power

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