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Low Power Synthesis Methodology for Fixed Point FIR Filter Using LCCSE Method

S. Sangeetha, R. Nandhakumar


We present a novel finite-impulse response(FIR) filter synthesis technique that allows for aggressive voltage scaling by exploiting the fact that all filter coefficients are not equally important to obtain a ―reasonably accurate‖ filter response .Our technique implements a level constrained common subexpression elimination algorithm, where we can constrain the number of full adder levels(ALs) required to compute each of the coefficient outputs. By specifying a tighter constraint (in terms of the number of adders in the critical path) on the important coefficients, we ensure that the later computational steps compute only the less important coefficient outputs. In case of delay variations due to voltage scaling and/or process variations, only the less important outputs are affected, resulting in graceful degradation of filter quality. The proposed method we are using lccse algorithm, to reduce the adder level and also power and area to compute each of the coefficients output. In proposed work, we are using conditional carry adder to reduce computational complexity of FIR filter and also reduce the power and area. The average power savings of 25%-30%.


Finite–Impulse Response (FIR) Filter Synthesis, Low Power Methodology, Variation Aware Design.

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K.Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.

D.R.Bull and D. H. Horrcks, ―Primitive operator digital filters,‖ Proc.Inst. Elect. Eng.—Circuits Devices Syst., vol. 138, no. 3, pp. 401-412,Jun. 1991.

A. G. Dempster and M. D. Macleod, ―Use of minimum-adder multiplier blocks in FIR digital filters,‖ IEEE Trans. Circuits Syst. II, Analog Digit.Signal Process., vol. 42, no. 9, pp. 569-577, Sep. 1995.

H.J. Kang and I.-C. Park, ―FIR filter synthesis algorithms for minimizing the delay and the number of adders,‖ IEEE Trans. Circuits Syst. II, AnalogDigit. Signal Process., vol. 48, no. 8, pp. 770-777, Aug. 2001.

A.Dempster et al., ―Designing multiplier blocks with low logic depth,‖in Proc. ISCAS, May 2002, vol. 5, pp. 773-776.

Y.Takahashi and M. Yokoyama, ―New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination,‖ in Proc. ISCAS, May 2005, vol. 2, pp. 1445-1448.

C.Yao et al., ―A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters,‖ IEEE Trans. Circuits Syst. I, Reg.Papers, vol. 51, no. 11, pp. 2211-2215, Nov. 2004.

A. Hosangadi et al., ―Algebraic methods for optimizing constant multiplications in linear systems,‖ J. VLSI Signal Process. Syst., vol. 49, no. 1,pp. 31-50, Oct. 2007.

O. Gustafsson and L. Wanhammar, ―ILP modelling of the common sub-expression sharing problem,‖ in Proc. 9th IEEE ICECS, Dec. 2002, vol. 3,pp. 1171-1174.

S.Vijay et al., ―A greedy common subexpression elimination algorithm for implementing FIR filters,‖ in Proc. ISCAS, May 2007, pp. 3451- 3454.


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