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High Speed Low Power Viterbi Decoder using M-Algorithm

P. Sangeetha, J. Muralidharan


High speed, low power design of viterbi decoder for Trellis Coded Modulation (TCM) systems. In this paper it is well known that the Viterbi Decoder(VD) is the dominant module determining the overall power consumption of TCM decoders. Precomputation architecture incorporated with T-algorithm for VD is proposed, which can effectively reduces the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in this paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption without performance loss, while the degradation in clock speed is negligible. T-algorithm is used only for finding the path metrics. But M-algorithm is used to find the PMs of the feedback loop also. So modified TCM decoder is designed using M-algorithm. The power consumption is reduced by using the M-algorithm and speed also increased.


Trellis Coded Modulation (TCM), Viterbi Decoder, VLSI.

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