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Design and Development of Output Response Analyzer for the BIST of Sigma-Delta Modulator

Ritika Upadhyay, Anil Kumar Sahu


Testing of high resolution second order sigma delta (ƩΔ) modulator is a very expensive process. With the advanced technology, where the complexity over a small area is increasing, then testing at low cost with good accuracy is becoming a tedious issue for the manufacturing process. The cost effectiveness can be calculated on the basis of different parameters of the ƩΔ modulator such as SNDR, ENOB, Gain, Offset, THD, SNR etc. Testing time also play an important role in the cost effectiveness of the modulator. The Built-in-self-test (BIST) allows the machine or circuit to test itself. BIST is desirable for the VLSI system in order to reduce the cost per chip of production –time testing by the manufacture, it can also provide the means to perform in-the field diagnostic. Therefore, this paper will demonstrate a possibility to simplify modeling and simulation of testing strategy of high-resolution ƩΔ modulator using MATLAB SIMULINK environment. Here, we are finding the cost effectiveness on the basis of Signal to Noise Distortion Ratio (SNDR) for the ƩΔ modulator BIST. A ƩΔ modulation based signal generator is considered which can produce analog sinusoidal test stimuli and digital reference signal on chip. By comparing the ADC output with that of the generator reference signal, the parameter can be determined on chip based on the standard equations in the proposed simulation environment.


Sigma-Delta Modulator (ƩΔ); Signal-to-Noise Ratio (SNR); Output Response Analyzer (ORA); Integrated Nonlinearity Error (INL); Built-in-Self Test (BIST); Dynamic Nonlinearity Error (DNL);

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