Email this article 
Open Access
Subscription or Fee Access
Performance Comparison of Different Asynchronous Design Methodologies
Abstract
Today, synchronous circuits are being operated at very high clock frequency. With this frequency high speed of electronics devices has increased but at the cost of power dissipation. In synchronous design having millions of transistors, single clock is to be supplied to all the components. Thus, maximum speed of the device is considered by the slowest component in the block. In this way synchronous design is also having a speed constraint. To overcome these problems, asynchronous design can be a solution. Various techniques are prevailing to make design asynchronous namely handshaking, clock gating and Globally Asynchronous and Locally Synchronous (GALS). Apart from these techniques, edge detection based technique is also introduced in this paper.
Keywords
References
Q. Wu, M. Pedram, and X. Wu.Clock-gating and its ap-plication to low power design of sequential circuits. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 47(103) 415-420, Mar. 2000.
A. J. Martin and M. Nystrom, “Asynchronous techniques for systemon- chip design,” Proc. IEEE, vol. 94, no. 6, pp. 1089–1120, Jun. 2006.
V. Tiwari et al., “Reducing Power in High-Performance Microproces- sors,” 35th DAC, June 1998.
J Kathuria, M Ayoubkhan, A Noor, "A Review of ClockGating tech- niques," MIT International Journal of Electronics and Communication Engineering, vol. 1, pp. 106-114, Aug 2011.
R. Cassia, F. Franca and V. Alves, "Synchronous to Asynchronous Con- version of Digital Circuits", 2006 Ph.D. Research in Microelectronics and Electronics, 2006.
M. Krstic, E. Grass, F. K. Gurkaynak, and P. Vivet, “Globally asyn- chronous, locally synchronous circuits: Overview and outlook,” IEEE Des. Test Comput., vol. 24, no. 5, pp. 430–441, Sep./Oct. 2007.
J.Becker, M.Huebner, M.Ullmann,"Power Estimation and Power measure- ment of Xilinx Virtex FPGAs:Trade-offs and Limitations", 2003, IEEE Procedings of the 16th symposium on integrated circuits and system designs.
A.kumar, Fundamentals of digital circuits. Delhi: PHI learning, 2009.
L. Donald, P albert, G. saha,Digital principles and applications. Delhi: McGraw-Hill, 2000.
H. Katabami, H. Saito and T. Yoneda, "Design of a GALS-NoC Using Soft-cores on FPGAs," Embedded Multicore Socs (MCSoC), 2013 IEEE 7th International Symposium on, Tokyo, 2013, pp. 31-36.
J. M. Chabloz and A. Hemani, "Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links," 2012 25th International Conference on VLSI Design, Hyderabad, 2012, pp. 191-196.
M. Fattah, A. Manian, A. Rahimi and S. Mohammadi, "A High Throughput Low Power FIFO Used for GALS NoC Buffers," 2010 IEEE Computer Society Annual Symposium on VLSI, Lixouri, Kefalonia, 2010, pp. 333-338.
F. Burns, D. Sokolov and A. Yakovlev, "GALS synthesis and verification for xMAS models," 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, 2015, pp. 1419-1424.
L. Sterpone, L. Carro, D. Matos, S. Wong and F. Fakhar, "A new reconfigurable clock-gating technique for low power SRAM-based FPGAs," 2011 Design, Automation & Test in Europe, Grenoble, 2011, pp. 1-6.
J. Shinde and S. S. Salankar, "Clock gating — A power optimizing technique for VLSI circuits," 2011 Annual IEEE India Conference, Hyderabad, 2011, pp. 1-4.
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.