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Built in Self Test Architecture Using Orthogonal Code Convolution for Device under Test

M. Nithyajeevi, R. Udaiya Kumar, S.Vimal Raj


This paper is aimed at testing a device under test (DUT) with embedded built-in self- test (BIST) capability. The embedded BIST technique has the capability to satisfy specified testability requirements and to generate the lowest-cost with the highest performance implementation. Linear Feedback Shift Register (LFSR) is used to replace the expensive testers to generate pseudo random test pattern to DUT while Orthogonal Code Convolution method acts as output compact analyzer and is able to compact the DUT output response into a manageable signature size. DUT with BIST capability contributes additional 30% hardware overhead but is somehow reasonable considering the test performance obtained. The ability of the BIST block provides high fault coverage. Moreover to increase the fault coverage parity bit is introduced for error checking. To overcome power dissipation clock gating is proposed to reduce number of transitions during off state so that clock signals can be kept in sleep mode to reduce power consumption.


automatic test-pattern generation (ATPG),BIST,PCBs.

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