Minimization of Area in Carry Select Adder

Abstract

The Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope of reducing the area consumption in the CSLA. This work uses a simple and efficient gate-level modification technique to reduce the area of the CSLA. Based on this modification 8-, 16-, 32-, 64- and 128-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area as compared to the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area and their products by hand with logical effort and through custom design and layout in 0.18-um CMOS process technology. The result analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.