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Design of 4-Bit Ripple Carry Adder Using Modified-GDI Technique

Poonam Dhruwe, Chandrahas Sahu


This paper present a new design technique, Modified Gate Diffusion Input (M-GDI) based on basic GDI cell. M-GDI technique is much more power efficient than existing GDI cell. This technique is used for design of fast, low power circuits, using reduced number of transistors, while improving power characteristics. In this paper a 4-Bit Ripple Carry Adder has been designed using M-GDI logic which reduces the number of transistor count significantly, while maintaining low complexity of design. The performance characteristics of M-GDI Ripple Carry Adder are compared with GDI and traditional CMOS logic. The simulation of the proposed design has been carried out in LT spice tool using 50nm technology.


Full Adder, GDI, Low Power, Modified-GDI, Ripple Carry Adder, Transistor Count.

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M.PEDRAM, R.MEHROTRA & XUNWEI WU (Oct 1997) “Comparison Between NMOS Pass Transistor Logic Style vs. CMOS Complementary Cells”, IEEE International Conference On Computer Design: VLSI In Computer & Processor.

SIMRAN KAUR, BALWINDER SINGH and D.K. JAIN (2015) “Design and Performance Analysis of Various Adders and Multipliers using GDI technique” International Journal of VLSI design & Communication System Vol.6, No.5, October 2015.

A.MORGENSHTEIN, A.FISH & WAGNER (2002) “GDI- A Technique For Low Power Design Of Digital Circuit: Analysis And Characterization”, IEEE International Symposium On Circuit & System.

P.BALASUBRAMANIUN & J.JOHN (Sep 2006) “Low Power Digital Design Using Modified GDI Method”, IEEE International Conference On Design & Test Of Integrated System In Nanoscale Technology.

S.HIREMATH & D, KOPPAD (Oct 2012) “Low Power Full Adder Circuit Using Gate Diffusion Input Mux”, 4th International Conference On Control & Embedded System.

SHOFIA RAM & R.R. AHAMED (July 2013) “Comparison And Analysis Of Combinational Circuit Using Different Logic Styles”, 4th International Conference On Computing, Communication & Networking Technologies.

S.ARCHANA & G.DURGA (Apr 2014) “Design Of Low Power And High Speed Ripple Carry Adder”, International Conference On Communication & Signal Processing.

K.DHAR, A.CHATTERGEE, S.CHATTERGEE (2014) “Design Of An Energy Efficient, High Speed, Low Power Full Subtractor Using GDI Technique”, IEEE Conference On Technology Symposium.

ATUL KUMAR & RAJEEVAN CHANDEL (2011) “Analysis of Low Power, High Performance XOR gate using GDI Technique”, International Conference on Computational Intelligence & Communication System.

R.MEHRA & A. VERMA (APR 2013) “Design and Analysis of Conventional and Ratioed CMOS Logic Circuit”, IOSR Journal of VLSI and Signal Processing, Vol.2, Issue 2, Mar-Apr 2013, PP 25-29.

R.UMA & P. DHAVACHELVAN (2012) “Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits”, 2nd International Conference on Communication, Computing & Security.

PANKAJ VERMA & RUCHI SINGH (OCT 2013) “Modified GDI Technique-A Power Efficient Method For Digital Circuit Design”. International Journal of Advanced Technology in Engineering and Science Vol. 01, Issue No.10.

POOJA VERMA & R. MANCHANDA (FEB 2014) “Review of Various GDI Techniques for Low Power Digital Circuits”, International Journal Of Emerging Technology and Advanced Engineering Vol. 4, Issue 2, Feb 2014.

ZIMMENNAN R., FICHTNER W., "Low-power logic styles: CMOS versus pass- transistor logic", IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, 1997.

R.UMA & P. DHAVACHELVAN (2013) “Low Power and High Speed Adders in Modified Gate Diffusion Input Technique”, @Springer.


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