FPGA Implementation of Floating Point Modules for Evaluating Accurate Arithmetic Expression and DSP Applications
Recently implementation of floating point modules on FPGA provides acceleration for various applications that requires high performance and high precision floating point arithmetic. Floating point arithmetic in DSP is a more flexible and general mechanism than fixed point. With floating point, system designers have access to wider dynamic range. Today many of the scientific problems are concerned with high precision and energy-efficient floating point arithmetic. With the aim of achieving high precision results and to optimize the speed, in this paper architectures were developed for the evaluation of arithmetic expression using pipelined floating point modules in IEEE 754 formats. Experimental results showed the proposed design resulted in high clock rates compared to the straightforward implementation of floating point module tree architecture and a comparative study was made between SPARTAN 3E and VIRTEX II PRO devices. Additionally the designs can be extended to evaluate general expressions as well as multiple expressions. Such expression evaluations were widely used in embedded computing and digital signal processing applications.
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