A Fast Locking ADPLL for Power Reduction through Feed Forward Compensation Technique
Xin Chen, Jun Yang,” A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique” IEEE Trans. Very Large Scale Integration(VLSI Systems), vol. 19, no. 5 pp. 857–869, May 2011.
R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 50, no. 11, pp. 815–828, Nov. 2003.
P.-L. Chen, C.-C. Chung, and C.-Y. Lee, “A portable digitally controlled oscillator using novel varactors,” IEEE Trans. Circuits Syst. II,Exp Briefs, vol. 52, no. 5, pp. 233–237, May 2005.
C.M. Hsu, M. Z. Straayer, and M. H. Perrott, “A low-noise wide-BW 3.6-GHz digital _ fractional-N frequency synthesizer with a Noiseshaping time-to-Digital converter and quantization noise cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776–2786,Dec 2003.
H.Lee,A.Bensal,:Y.Frans J.Zerbe,S.Sidiropoulos and M.Horowitz,” Improving CDR performance via estimation”,in IEEE ISSCCDig. Tech papers 2006,pp. 1296-1303.
J. Lee and B. Kim, “A low-noise fast-lock phase -locked loop with adaptive andwidth control,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp.1137-1145,Aug 2000.
Kratyuk, V. and Hanumolu, P. K. “A Design Procedure for All Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked Loop Analogy”, IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 54, No. 3, pp.247–251,2007.
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.