FPGA Implementation of Digit-Serial Architecture for Various Digit-Size and Wordlength in Viterbi Decoder

Abstract

Convolutional code is an essential Forward Error Correcting (FEC) code for many wireless communication systems. Viterbi decoder is an optimal algorithm for decoding a convolution code. The design of an efficient Integrated Circuit (IC) in terms of power, area and speed simultaneously has become a challenging problem. Power dissipation is recognized as a critical parameter in modern Very Large Scale Integrated circuit (VLSI) design field. The major source of power dissipation is dynamic power dissipation, which is due to the total switching activity. Viterbi decoder employed in digital wireless communication is complex and dissipates large power. The proposed method focuses on power reduction of Viterbi decoderat architecture level. The proposed method is to obtain high speed and low power Viterbi decoder using digit-serial architecture for various digit size and word length. In the digit-serial architecture N bits are processed per clock cycle and a word is processed per W/N clock cycles (W-word length, N-digit size). Digit-serial architecture achieves high speed and low power. Viterbi decoder is designed with code rate k/n=¼, constraint length K= 3, word length W=8, 32 and digit size N=2, 4. The functionality is simulated and verified using Modelsim and synthesized using Xilinx FPGA SPARTAN3.