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Design of Low Power 8 Bit Carry Select Adder Using 14T Transistor 1 Bit Adder

Pooja Chawhan, Akanksha Sinha


In digital electronic, adder is most important fundamental in wide variety of digital system. There are among the fast adder exist, but fast adding using less area, delay and power consumption is still challenging of digital media. The design of integrated circuit, are occupancy play most important role because increasing the necessary of portable system. The carry select adder is one of the speediest adders used in many data processing processors to perform fast arithmetic operation. The carry select structure is required more area and power because its internal structure is consist of duel ripple carry adder and multiplexer. The moderns design of carry select adder requiring a reduction size and less power consumption. the logic function involve the 3-T-XOR gate, regular  8 bit CSLA and modified 8 bit CSLA are analyzed to the power consumption and power delay product are identified. In this project, the proposed design using 14T  transistor 1bit adder is used to design of 8 bit carry select adder has reduced the transistor count and provide  lesser power consumption as well as power delay product as compared to the 3-T-XOR gate and regular 8 bit CSLA. The main advantage of proposed design of 8 bit carry select adder using 14-T transistor 1bit adder provide lesser power consumption and power delay product. The simulation result is carried out using mentor graphic tanner EDA 16.3 version tool and BISM4 90nm CMOS technology.


Carry Select Adder, Low Power Design, 14T Transistor 1bit Adder, Nanometre Technology.

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