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Dynamic Operand Interchange in Reconfigurable Modified Baugh-Wooley Multipliers for Dynamic Power Minimization

Aswathy Sudhakar, D. Gokila


VLSI implementation of multipliers should be in such a way that it reduces the redundancy caused by the repetition of multiplier modules for different functionalities, as redundancy causes area overhead as well as speed degradation. In this paper, the comparison of various multiplier architectures is made and Baugh-Wooleyarchitecture is found as the best suited multiplier for VLSI implementation. The conventional multiplier architecture of Baugh-Wooley is modified to obtain an improvement of speed by (6-15) %. Also Baugh-Wooley multiplier gives an area reduction by 40% and also with (3-5)% power reduction. The reconfiguration on Baugh-Wooley multiplier (BW) is then explained with respect to the optimum reconfiguration constraints. The large speed overhead caused by reconfiguration limits it from being used in practical applications which are overcome by using pipeline registers. Effective use of pipeline registers is made so as to control the speed overhead problem occurring through the reconfiguration of multiplier functionalities. To filter out the unnecessary switching power,Dynamic Operand Interchange (DOI) technique is applied. The results are compared between non-reconfigurable, non reconfigurable pipelined and reconfigurable 8-stage pipelined modified BW multiplier architectures for n=8, 16, 32, and 64. It is obtained that the Partial Run-Time Reconfiguration reduces the area by 31-40%.Pipelining improves the speed by 4-5 times whereas run-time reconfiguration with DOI results in 5-15% reduction in overall power dissipation.


Baugh-Wooley Algorithm, 2-D pipeline gating, Partial Reconfiguration, Dynamic Operand Interchange.

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