Design of Various PFD and Charge-Pump Architectures for a PLL- a Survey
Jayashree Nidagundi,Harish desai,“Design and Implemetation of low power phase frequency detector”,IJSET,vol.2 Issue 3,pp.160-163 April 2013.
MozhganMansuri,Dean Liu, “Fast Frequency Acquistion Phase frequency Detectors for Gsample/s phase locked loops”,IEEE journal of solid state circuits,vol.37,No.10,oct 2002.
Md Monirul Islam and Ankit shivhare, “The design of a low power floating gate based phase frequency detector and charge pumpImplementation ”International Journal of VLSI design andcommunicationsystems(VLSICS) vol.4,No.2,April 2013.
VaijayantiLule and V.G.Nasre, “Low power 0.18um CMOS Phase frequency detector”,IJETAE vol.2,Issue 7,July 2012.
Jyoti Gupta,Ankur Sangal, “High speed CMOS charge pump circuit for PLL application using 90nm CMOS technology”,Middle East journal of Scientific and Research,2012.
Xintain Shi,Kilian Imfeld,Steve tanner, “A low jitter and low power CMOS PLL for Clock Multiplication”,IEEE Esscirc_Mixed signal high voltage and high power circuits7,2006.
Woogeun, “Design of high performance CMOS charge pumps in phase locked loops, IEEE,1999.
Ching-Lung Ti,Yao-Hong Liu, “A 2.4-Ghz Fractional-N with a PFD/CP Linearization and an Improved CP circuit”,IEEE,2008.
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