Design of Various PFD and Charge-Pump Architectures for a PLL- a Survey

Abstract

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. This paper presents the survey of the performance of several architectures for the Phase Frequency Detector (PFD) and Charge Pump (CP). PFD plays a significant role on the whole Phase Locked Loop system (PLL). PFD has an advantageous function over the Phase detector (PD) and Frequency detector (FD) by detecting phase and frequency detection at a time. The performance of charge pumps depends heavily on the ability to efficiently generate high voltages on-chip while meeting stringent power and area requirements.