High Speed Area Efficient VLSI Structure for Real Time Image Computing
A VLSI architecture capable of real-time 2-D Discrete Wavelet Transform computing is proposed in this paper. The proposed architecture-- based on a new and fast convolution approach-- reduces the hardware complexity and a reduction in the critical path of the multiplier block. The architecture with an efficient utilization of memory area, produces one output in every clock cycle. As a result, real time DWT computation is feasible. The system is verified - using JPEG2000, on Xilinx Virtex-II Field Programmable Gate Array (FPGA) device without accessing any external memory.For an image size of 256x256 pixel a computation rate more than 270Msamples/s and a memory requirement of lessthan 16kb is the outcome of the proposed model. The proposed design requests reduced memory and provide very high-speed processing as well as high PSNR quality.
Mallat,S, ”A Theory for Multiresolution Signal Decomposition: The Wavelet Representation”, IEEE Trans. on Pattern Analysis and Machine Intelligence, Vol. 11, No. 7. (1989) 674-693W.-K. Chen, Linear Networks and Systems (Book style). Belmont, CA: Wadsworth, 1993, pp. 123–135.
Gnavi, S., Penna, B., Grangetto, M, Magli, E., Olmo, G,”Wavelet kernels on a DSP: A comparison between lifting and filter banks for image coding”, Applied Signal Processing: Special Issue on Implementation of DSP and Communication Systems. Vol. 2002. No. 9. (2002) 981-989.
Daubechies, I., Sweldens, W,” Factoring wavelet transforms into lifting schemes”, The Journal of Fourier Analysis and Applications. vol. 4. (1998) 247-269.
Acharya, T., Tsai, P.S,” JPEG2000 Standard for Image Compression”, A John Wiley & Sons, Inc. USA (2005).
Andra, K., Chakrabarti, C, Acharya,T,” A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform”, IEEE Transactions on Signal Processing, vol. 50. No. 4. (2002) 966-977.
Andra, K., Acharya,T., Chakrabarti, C.” A High- Performance JPEG2000 Architecture”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 13. No. 3. (2003) 209-218.
B.-F.Wu and C.-F. Lin, “An efficient architecture for JPEG2000 coprocessor,” IEEE Trans. Consum. Electron., vol. 50, no. 4, pp. 1183–1189, Nov. 2004.
H.-C. Fang, C.-T. Huang, Y.-W. Chang, T.-C.Wang, P.-C. Tseng, C.-J. Lian, and L.-G. Chen, “81 MS/s JPEG2000 single-chip encoder with rate-distortion optimization,” in Proc. ISSCC Tech. Dig., 2004, vol. 1, pp. 28–531.
Q. P. Huang, R. Z. Zhou, and Z. L. Hong, “Low memory and low complexity VLSI implementation of JPEG2000 codec,” IEEE Trans. Consum. Electron., vol. 50, no. 2, pp. 638–646, May 2004.
K. Z. Mei, N. N. Zheng, C. Huang, Y. Liu, and Q. Zeng , “VLSI Design of a High-Speed and Area-Efficient JPEG2000 Encoder,” IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 8, pp. 1065–1078, Aug. 2007.
JPEG2000 Decoder: BA109JPEG2000D Factsheet.Barco-Silex. (2008).
Acharya, T., Chen, P,” VLSI Implementation of a DWT Architecture”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). Monterey, CA. (1998).
Acharya, T,”Architecture for Computing a Two-Dimensional Discrete Wavelet Transform”, US Patent 6178269. (2001).
N.D. Zervas, G.P. Anagnostopoulos, V. Spiliotopoulos, Y. Andreopoulos, C.E. Goutis, “Evaluation of design alternatives for the 2-D-discrete wavelet transform,” IEEE Trans. Circuits Syst. Video Technol., Vol.11, no. 12, pp. 1246–1262. Dec. 2001.
G. Dimitroulakos, M.D. Galanis, A. Milidonis, and C.E. Goutis, "A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000," INTEGRATION, the VLSI journal., vol. 39, no. 1, pp. 1-11, 2005.
VirtexTM-II platform FPGAs: Complete Data Sheet. Xilinx. (2007).
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.