Open Access Open Access  Restricted Access Subscription or Fee Access

Design of Low Power High Performance Parallel-Prefix Adders

K. Saranya

Abstract


The necessity of designing high speed and low power arithmetic circuits suitable for computationally intensive applications has motivated the design of a high performance arithmetic unit using high speed parallel prefix adder architectures. The present work comprises of designing high performance low power adders. Ling and kogge stone adder is designed for power analysis based on parallel prefix adder structure. For the present work, 0.125μm technology has been used. The average power consumed of the both the adders is found at a supply voltage of 5V.From the analysis made Ling adder is found to consume less power than the kogge stone adder. Ling adders designed based on the ling’s algorithm. The whole simulation has been done using TSPICE S-Edit.

Keywords


Arithmetic Unit, Kogge-Stone Adder, Parallel Prefix Structure, Ling Adder.

Full Text:

PDF

References


Bart.R. Zeydel, Dursun Baran and Vojin, Oklobdzija.G (2010) “Energy-Efficient Design Methodologies: High performance VLSI Adders” IEEE J. Solid-State Circuits,vol.45,No6.

Giorgos Dimitrakopoulos and Dimitris Nikolos(2005),” High-Speed Parallel-Prefix VLSI Ling Adders” IEEE Transcations on computers, Vol. 54, no. 2, Feb,pp.225-231.

Kogge.P.M and Stone.H.S,(1973) “A parallel algorithm for the efficient solution of a general class of recurrence equations”, IEEE Trans. Computers Vol. C-22, No. 8, Aug., pp.786-793.

Oklobdzija.V.G, Zeydel.B.R, Dao.H.Q, Mathew.S, R.Krishnamurthy,(2005) "Comparison of High-Performance VLSI Adders in Energy-Delay Space", IEEE Transaction on VLSI Systems, in press.

Ramanathan.P, Vanathi.P.T,(2009) “A Novel Power Delay Optimized 32-bit Parallel Prefix Adder For High Speed Computing” International Journal of Recent Trends in Engineering, Vol 2, No. 6, November.

Radu Zlatanovici, Member, IEEE, Sean Kao, and Borivoje Nikolic(2009),” Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example” IEEE Journal of Solid-State Circuits, VOL. 44, NO. 2, Feb.

Rabaey.J,(2003) Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall.

Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy and Hiranmay Saha,” Design of High Performance Low Power 16 Bit Arithmetic Units Using Kogge-Stone Parallel Prefix Adder Architectures, Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India,Vol.2,1.

Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, and Kaushik Roy,(2010) Fellow, IEEE, “Voltage Scalable High-Speed Robust Arithmetic Units Using Adaptive Clocking,”IEEE Trans. Very Large Scale Integr (VLSI) SYSTEMS,pp.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.