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Power Efficient Adaptive FIR Filter Design for Low Power DSP Applications

P. Dhanya

Abstract


This paper presents the design of power efficient adaptive finite impulse response (FIR) filters where the filter order can be dynamically changed. The filter order can be changed by detecting the amplitude of the input samples and filter coefficients. The power consumption depends upon the filter order. In existing system coefficients are not programmable. An adaptive filtering is employed in proposed approach by means of Least Mean Square Algorithm (LMS).It uses feedback in the form of an error signal, which will again send to the amplitude detection logic and accordingly coefficient will get modified in order to get the desired output. Amplitude Detection (AD) block is used to detect the amplitude of the input signal. We can dynamically change the filter order by turning off some multipliers. The amount of computation and the corresponding power consumption of FIR filter are directly proportional to the filter order. significant power savings can be achieved, if the amplitude of input x(n)abruptly changes for every cycle then multiplier will be turned on and off continuously. Multiplier control decision window is used to solve the switching problem using ctrl signal generator inside MCSD. The number of input samples consecutively smaller than xth are counted and the multipliers are turned off only when m consecutive input samples are smaller than xth. The proposed scheme will improve the performance of the filter with the improvement in the power savings.

Keywords


Adaptive Filtering, AD, FIR Filter, LMS, MCSD

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References


Seok-jae Lee,Student member ―A Recofigurable FIR Filter Architecture to Trade off Filter Performance for Dynamic Power Consumption‖,vol.19,Dec 2011.

J. Ludwig, H. Nawab, and A. P. Chandrakasan, ―Low power digitalfiltering using approximate processing,‖ IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 395–400, Mar. 1996 .

A. Sinha, A. Wang, and A. P. Chandrakasan, ―Energy scalable design,‖ IEEE Trans Very Large Scale Integr. Syst., vol. 10, no. 2, pp. 135–145, Apr. 2002.

K.-H. Chen and T.-D. Chiueh, ―A low-power digit-based reconfigurable FIR filter,‖. IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53 no. 8, pp. 617– 621 Dec.2006

O.Gustafsson, ―A difference based adder graph heuristic for multipleconstant multiplication problems,‖ in Proc. IEEE Int. Symp. CircuitsSyst., 2007, pp. 1097–1100.

R. I. Hartley, ―Subexpression sharing in filters using canonical signed digit multipliers,‖ IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp. 677–688, Oct. 1996.

S. H. Nawab, A. V. Oppenheim, A. P. Chandrakasan, J. M. Winograd, and J. T. Ludwig, ―Approximate signal processing,‖ J. VLSI Signal Process., vol. 15, no. 1–2, pp. 177–200, Jan. 1997


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