Circuit-Level Model of Dual-Gate Bi-Layer and Multi-Layer Graphene Fet
This paper presents Circuit level model of a dual gate bilayer and four layers GFET. This model accurately estimates the conductance at the charge neutrality point (CNP). At the CNP, the device has its maximum resistance, (i) Validates the device off-current for a range of Electric field perpendicular to channel (ii) Estimates the amount of bandgap opening created by application of Electric field using the general Schottky equation. (iii) Validates the channel output conductance against varying gate voltage for both a bilayer and four layer graphene channels.
Ime J. Umoh, Student Member, IEEE, Tom J. Kazmierski, Senior Member, IEEE, and Bashir Al-Hashimi, Fellow Member, IEEE. Multi-layer graphene FET compact circuit-level model with temperature effects.
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