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A Low Power VLSI Architecture Design Using Enhanced ADPLL

T.M. Sathish Kumar, Dr.P. S. Periasamy, C. Divya


This paper describes the design and implementation of an ADPLL by using Fuzzy logic. The digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The ADPLL is built entirely from logic circuits and has replaced the classical DPLL in many applications, especially digital communications. The project is to reduce the power and improve the tuning range of frequency.To reduce power the System on Chip is used. The proposed ADPLL is designed using Tanner EDA Tool.


All Digital Phase Locked Loop (ADPLL), Phase Frequency Detector (PFD), Time-to-Digital Converter (TDC), Frequency Divider, Digitally Controlled Oscillator (DCO), Programmable Divider, Fuzzy Inference Symbol.

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