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Design of GDI Based Full Adder Circuit for Low Power Applications
Abstract
Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units. Due to scaling trends and portability of electronic devices there is a high demand and need for low power and high speed digital circuits with small silicon area. So, design and analysis of low power and high performance adders are of great interest and any modification made to the full adder circuit would affect the performance of the entire system. This paper describes the design and analysis of GDI based 1-bit full adder circuit for low power applications. GDI technique is used to reduce power consumption, propagation delay while maintaining low complexity of logic design. Here we have introduced a 11-T GDI based full adder circuit which can be used for low power applications. The proposed circuit is better than the existing technique in terms of average power and speed with minimum area penalty. Simulations are based on BPTM model and have been carried out by Tanner EDA tool on 180nm, 90nm, 65nm and 45nm technology.
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