A Non-Intrusive BIST Capability for UART

Abstract

As the device size is shrinking, device density is increasing. This increases the functional complexity on the chip and also accessing of internal sub-circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip which has become very compulsory is a very time consuming and costly process with increasing cost. The term “functional BIST” describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within other parts of the system. Built-In Self-Test (BIST) techniques which are non-intrusive to the circuitry under test are investigated for incorporation in UART. In this paper, the analysis of area overhead and increase in delay for implementing non intrusive BIST technique in UART is carried out. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production. Hence a UART with BIST has the objectives of firstly to satisfy specified testability requirements, and secondly to generate the lowest-cost with the highest performance implementation. We have implemented Universal asynchronous receiver transmitter (UART) with Non-intrusive BIST capability using LFSR techniques and compared these techniques for the logic utilization in SPARTAN2E XC2S300-PQ208 FPGA device.