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A Case Study on Various Clock Routing Algorithms
Abstract
The nature of Clock Tree Synthesis (CTS) in complex hierarchical designs decides timing closure, power dissipation, area of chip and interconnect length. CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to minimize skew and insertion delay. Apart from these, useful skew is also added in the design by means of buffers and inverters. Various clock routing algorithms have been studied in this paper.
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References
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