Implementation of Body Driven Double Tail Dynamic Comparator for High Speed and Low Power ADC’s

Abstract

The ultra- low power and area efficient analog –to- digital converters (ADCs) makes use of low voltage CMOS dynamic comparators to maximize the power efficiency and speed. The conventional dynamic comparators have characteristics like high input impedance, no static power dissipation and good robustness against noise and mismatch. The drawback is that large numbers of transistors are used to reduce the offset, so the speed of the comparator is minimized. Double tail comparators overcome the drawbacks in conventional comparator by reducing the stacking of transistors with low supply voltage and delay. But there is a problem of    low trans-conductance for this comparator. In modified double tail comparator, few transistors are added and the positive feedback in the regeneration stage is strengthened and the power consumption and delay time is reduced. In this paper delay analysis of dynamic double tail comparators are presented with respect to speed and supply voltage.  Then based on the delay analysis results, the modified double tail dynamic comparator is modified in terms of architecture and transistor technology which results  as body driven  Double Tail  Dynamic Comparator  for fast operation even in ultra low supply voltages. Simulation results can be done by using 180nm CMOS technology reveals that the delay time is considerably reduced.