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Design of SISO Shift Register by Using Pulse Triggered Flip-Flop for Effective Area and Power Minimization at 32nm Technology
Abstract
Power dissipation and area conservation is considered to be a vital issue while designing synchronous CMOS circuit. In this paper three types of four bit Serial In Serial Out (SISO) shift register is designed by using Pulse-Triggered Flip-Flop (P-FF). First design of shift register is simple and designed by using only P-FF. In Second type of shift register, clock gating technique is used to reduce the dynamic power dissipation and third type of shift register, common pulse generator is used which is efficient in terms of power as well as area. These shift registers are compared in terms of power and area in order to find better design. Design is implemented using CMOS 32nm BSIM4 Technology at schematic level with VDD = 0.9 V in Tanner EDA.
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