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Efficient and Optimized Reversible BCD Adder using DR Gate
Abstract
Reversible logic is becoming a most popular field and has vast opportunities such that it has been search that it is applicable in various technological department; such as in CMOS, nanotechnology and optical computing. This create an new effect in area of computation which teaches about computation. Quantum Computing results in operation and function. The reversible arithmetic designs are very effective regarding counting of reversible gates, delay and quantum cost. Design and timing constraint of all adders results in efficient processing. In this design we propound optimized BCD adders with the use of modified DR gate. The main moto of designing reversible gate is to low the cost of design so that we get required output and to decrease quantum cost, gate count, no. of delays. The main aim for designing this is to refunctioned the actual parameters and results in flexibility. This architecture has been stimulated in VHDL technology using tool as Xilinx ISE 14.7 and then it can executed in FPGA
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