Low Power Multiplier Design Using Feeder and Bypass Registers

Abstract

An important issue in the design of VLSI circuits is the choice of the basic circuits approach and topology for implementing various logic and arithmetic functions such as adders and multipliers. The majority of the real life application like microprocessor and digital processing implementations require the multiplier. Since multiplier is essential for many digital systems, the power reduction in multiplier becomes one of the most significant design parameter. To achieve such power reduction, modifications are made to conventional shift-and-add multiplier architecture and such low power structure called Bypass Zero Feed A Directly (BZ-FAD) architecture is proposed in this work. This architecture lowers the switching activity of conventional multiplier. The modification to multiplier include the removal of shifting of B register, Providing the data available in A directly to the adder, using a feeder register, bypass register, ring counter instead of binary counter and removal of partial product shift.