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A Novel Architecture for Test Pattern Generation in BIST
Abstract
Multiple test patterns varying in a single bit position is generated for Built-In-Self-Test (BIST). The test patterns generated using traditional techniques lacks in correlation between successive test patterns thereby causing excessive power dissipation. So, in order to improve correlation between the successive test patterns, the patterns were generated using twisted ring counter. The modified architecture has the required fault coverage with reduced test length. The area and power requirements are optimized by generating test patterns using modified architecture. The generated test patterns have an advantage of minimum transition sequence. This test pattern generation technique for BIST schemes is coded using VHDL and simulated using ModelSim 6.3f. The gate count and the power report were analyzed using Xilinx ISE 9.1 software.
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