A Survey on Single and Double Edge-Triggered Flip-Flops to Design Scan Flip-Flop Cell
This paper elucidates about different topologies of both SET&DET flip-flops and investigated under estimation of performance metrics like Power consumption, delay (D-Q), Area, Transistor Count, Number of Clocked Transistors, PDP and EDP extensively. Based on this survey a new low power, less area occupied, high performance Pulsed scan flip-flop cell is proposed.
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