Open Access Open Access  Restricted Access Subscription or Fee Access

Design and Analysis of Combinational Circuits Using Gate Diffusion Input

P. Usha, P. SivasankarRajamani

Abstract


The popularity and necessity of portable electronic systems by users have strongly influenced VLSI designers to make great effort for reduced silicon area, improved speeds, long duration battery life, and great reliability. The VLSI designers always try to save power consumption while designing a system.  This technique also reduces the transistor count and thus the area of the circuit. Thus the circuit will be much simpler and easy to manage. To design of an 8 – bit Arithmetic Logic Unit using Gate Diffusion Input (GDI) Technique and also the comparison with other logic styles. Basic Logic Gates, half adders, full adders, multiplexers etc are also designed and performances are compared in terms of power dissipation and transistor count. The ALU design uses 2x1 multiplexers, 4x1 multiplexers, half adders, full adders and OR gates to realise the basic arithmetic and logic functions. The arithmetic functions are Addition, Subtraction, Increment, and Decrement. The logic functions that can be realised are AND, OR, XOR, and XNOR. The simulation tool used is Tanner EDA 13.0 using 250nm technology.


Keywords


CMOS, GDI, XOR, XNOR, TANNER EDA

Full Text:

PDF

References


Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner “Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits” IEEE Transactions on Very Large Scale Integration (VLSI) systems, volume 10, no. 5, October 2014.

Chandrakasan A. P , Shang .S , and Brodersen R. W , “Low- power CMOS digital design,” IEEE Journal, Solid-State Circuits, volume 27, pp. 473– 484, April. 2012.

Chandrakasan A. P and Brodersen R. W “Minimizing power consumption in digital CMOS circuits,” Proceeding,. IEEE, volume 83, pp. 498–523, April. 2011.

Al-Assadi .W, Jayasumana A. P, and Y. K. Malaiya, “Pass-transistor logic design,” International, Journal, Electron., volume 70, pp. 739–749, 2011.

Abu-Khater I. S, Bellaouar .A, and Elmastry M. I, “Circuit techniques for CMOS low-power high-performance multipliers,” IEEE Journel, Solid- State Circuits, volume 31, pp. 1535–1546, October 2011.

“Gate-diffusion input (GDI)—“A novel power efficient method for digital circuits: A design methodology,” presented at the 14th International. ASIC/SOC Conference, Washington, DC, September 2001.

Chandrakasan A, Bowhill W. J, and Fox F, “Design of High Performance Microprocessor Circuits”, 2000, chapter 5, pp. 80–97

Morgenshtein A, Fish A, and Wagner I. A, “Gate-diffusion input (GDI)—a technique for low power design of digital circuits”: Analysis and characterization, submitted for publication

Zimmermann R and Fichtner W, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE Journal Solid-State Circuits, volume 32, pp. 1079–1090, June 1997.

Adler V and Friedman E .G , “Delay and power expressions for a CMOS inverter driving a resistive-capacitive load,” Analog Integral Circuits Signal Process., volume 14, pp. 29–39, 1997.

Yano K , Sasaki Y , Rikino K , and K. Seki, “Top-down pass-transistor logic ,” IEEE Journal Solid-State Circuits, volume 31, pp. 792–803, June 1996.

Chandrakasan A. P and Brodersen R. W,“ Minimizing power consumption in digital CMOS circuits,” Proc. IEEE, volume 83, pp. 498–523, April. 1995.

Weste N and Eshraghian K,” Principles of CMOS digital design” Reading, MA: Addison- Wesley, pp. 304–307.

Chandrakasan A. P., Sheng S , and Brodersen R. W, “Low- power CMOS digital design,” IEEE Journal, Solid-State Circuits, volume 27, pp. 473–484, April. 1992

Al-Assadi W , Jayasumana A. P , and Y. K. Malaiya, “Pass-transistor logic design,” International, Journel, Electron., volume 70, pp. 739–749, 1991

H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using XOR XNOR gates,” IEEE Transactions Circuits System. II, Analog and Digital Signal Processing., volume.49, no.1, pp. 25–30, January 2002.

J.-F. Lin, Y.-T. Hwang, M.-H. Sheu and C.-C. Ho, “A novel high speed and energy efficient 10 transistor full adder design,” IEEE Transaction Circuits Syst. I, volume 54, no. 5, pp. 1050–1059, May 2007.

Y. Jiang, Al-Sheraidah. A, Y. Wang, Sha. E, and J. G. Chung, “A novel multiplexer-based low-power full adder,” IEEE Transaction. Circuits System. II, Analog Digit. Signal Process., volume. 51, pp.345–348, July 2004.

H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using XOR XNOR gates,” IEEE Transaction. Circuits Syst. II, Analog and Digital Signal Processing., vol.49, no.1, pp. 25–30, Jan. 2002.

J.-F. Lin, Y.-T. Hwang, M.-H. Sheu and C.-C. Ho, “A novel high speed and energy efficient 10-transistor full adder design,” IEEE Transaction Circuits Syst. I, vol. 54, no. 5, pp. 1050–1059, May 2007.

Y. Jiang, Al-Sheraidah. A, Y. Wang, Sha. E, and J. G. Chung, “A novel multiplexer-based low-power full adder,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 51, pp.345–348, July 2004.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.