Reduction of Test Data Volume Based On Viterbi Compression Algorithm
Test vector compression has been an active area of research, yielding a wide variety of techniques. A test pattern compression scheme is proposed in order to reduce test data volume and application time. The proposed scheme finds a set of compressed test vectors using the Viterbi algorithm instead of solving linear equations. By assigning a cost function to the branch metric of the Viterbi algorithm, an optimal compressed vector is selected among the possible solution set. This feature enables high flexibility to combine various test requirements such as low-power compression and/or improving capability to repeat test patterns. The proposed on chip decompressor follows the structure of Viterbi encoders which require only one input channel. Experimental results compared with the dictionary algorithm compression. Dictionary based compression techniques are also popular in embedded systems domain. Since they provide a dual advantage of good compression efficiency as well as fast decompression mechanism. Viterbi algorithm provides better compression ratio compared to dictionary algorithm.
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