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Low Power 8TSRAM Design
Abstract
SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply
voltages. The conventional SRAM utilize 6 transistors. This cell has high power consumption due to false read operation. In order to improve stability, a half-select disturb free transistor SRAM cell is proposed. The existing cell is 6T SRAM. The proposed system utilizes this 6Tcell along with a decoupling logic. It utilizes a gated inverter SRAM cells to decouple the column select read disturb condition in half selected columns. This is one of the limitation to lowering the cell voltage. A false read operation is common in conventional 6T design due to bit select and word line timing mismatch. This is eliminated using the proposed 8T design. The design style analyzed is sense amp read based design. With the elimination of half select disturb, it is possible to enhance the overall array low voltage operability. Hence power consumption can be reduced by around 20%-30%. The tool used for simulation is Microwind.
Keywords
References
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