Open Access Open Access  Restricted Access Subscription or Fee Access

A Systematic Approach for Design of Compressed Test Data in SOC

R. Kathiresh, V.M. Ramprasath, M. Senthil Kumar

Abstract


An efficient Software/Hardware platform to execute
more number of programs the internal circuitry flow is considered. The data can be of bits-number of times the bits arriving with different time intervals. In this paper we illustrate about the compressed test data from the embedded cores in a system on a chip varies significantly during the testing process. A novel scheme has been implemented for compressed system on a chip testing based on
time-multiplexing for the channels. Some /more of the channels can be introduced which can enable the sharing the data channels, on which the compressed seeds are passed to every embedded core(individual cores). The channels can be fewer/larger based on the amount of testing channels available. The uses of modular and
scalable hardware for on-chip test control and test data compression have been used. We define an algorithmic model for test data compression that is applicable to system-on-chip devices comprising intellectual property-protected blocks.


Keywords


System on a Chip (SoC), Automatic Test Pattern Generation (ATPG), Automatic Test Equipment (ATE)

Full Text:

PDF

References


Adam B.Kinsman and Nicola Nicolicui, IEEE Member,“Approach of

multiplexed SOC designs”,pp-1159-1163,in Proc.IEEE Trans.

A.Wurtenberger and C.S.Tautermann,“A Hybrid Coding strategy for

optimized test data compression”,in Proc.IEEE,2003 PP.451-457.

E.H.Volkerink and S.Mitra,“Efficient seed utilization form reseeding

based compression”,in proc.,IEEE VTS-2003., pp.232-237.

A.Jas,B.Pouya and N.A.Touba,“Test data Compression technique for

embedding cores using virtual scan chains”, IEEE Trans.Comput.Aided

Design Vol.23,PP.775-781,Jul 2004.

P.T.Gonclari,B.M.Al-Hashimi,“Variable length input Huffman coding

for system-on-a-chip”, IEEE Trans.Comput.Aided Design

Integr.,vol22.pp.7873-789, Jun 2003.

C.V.Krishna and N.A.Touba,“Reducing test data volume using LFSR

resedding with seed compression”, in Proc.IEEE/ACM

Date.2004.,Vol.2,pp 321-327.

I.Pomeranz and S.M.Reddy,“Test data compression based on inputoutput

dependence”,IEEE Trans.Comput-Aided Design Integr.Circuits

Syst., Vol.22 ,no.5, pp.1450-1455,Oct.2003.

K.J.Balakrishnan and N.A.Touba, “Improving encoding efficiency for

linear decompressors using scan inversion”,in Proc. IEEE

ITC,2004,pp.936-944.

C.V.Krishna,A.Jas and N.A.Touba,“Test Vector encoding using partial

LFSR resedding”,in Proc.IEEE ITC,2001,pp.566-569.

Z.Wang,K.Chakrabarty and S.Wang, “SoC testing using LFSR

resedding and scan-slicebased RAM optimization and test

scheduling”,Proc.IEEE/ACM Date,pp.201-206,2007.

A.B.Kinsman and N.Nicolici,“Time-multiplexed test data

decompression architecture for core based SoC’s with improved

utilization of tester channels”,in Proc.IEEE ETS,2005,pp.196-201.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.