Open Access Open Access  Restricted Access Subscription or Fee Access

Design and Analysis of Furious Mechanism for Addition in Integers using Quaternary Signed Digit Number System

R. Sathishkumar, S.M. Dinesh, R. Divya, T.S. Athira

Abstract


With the binary system of numeration, the speed of arithmetic operations square measure restricted by formation and propagation of the carry. Mistreatment quaternary signed digit (QSD) system of numeration each carry free addition and borrow free subtraction are often achieved. The QSD system of numeration needs a special set of prime modulo based mostly logic for arithmetic operations. Employing a high base system of numeration like Quaternary Signed Digit, a carry free operation are often achieved. Arithmetic Operations like addition and subtraction for giant numbers like sixty four and 128 are often computed while not the propagation of carry mistreatment QSD system of numeration. Style is simulated and analyzed mistreatment 13.2 ISE machine.


Keywords


Quaternary Signed Digit (QSD).

Full Text:

PDF

References


T. Chattopadhyay, J.N. Roy, “Easy conversion technique of binary to quaternary signed digit and vice versa.” hysics Express, Vol. 1, No. 3, Pp. 165-174, 2011.

Behrooz Parhami, “Carry-Free Addition of Recoded Binary Signed- Digit Numbers”, IEEE Transactions on Computers, Vol. 37, No. 11, pp. 1470-1476, November 1988.

S. Hurst, “Multiple-valued logic -its status and its future”, IEEE trans.On Computers. Vol. C-33, no.12, pp. 1160-1179, 1984.

Reena Rani, Neelam Sharma, L.K.Singh, “Fast Computing using Signed Digit Number System” IEEE proceedings of International Conference on Control, Automation, Communication And Energy Conservation -2009, 4th-6th June 2009.

Reena Rani, Neelam Sharma, L.K.Singh, “FPGA Implementation of Fast Adders using Quaternary Signed Digit Number System” IEEE proceedings of International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009), pp 132-135, 2009.

Kawahito, S. Kameyama, “A 32 X 32 bit Multiplier using Multiple-valued MOS Current Mode Circuit”, Journal of Solid-State Circuits, IEEE, vol.1, pp.124 - 132, 1988.

Hanyu, M. Kameyama, “A 200 MHz pipelined multiplier using 1.5V-supply multiple valued MOS current-mode circuits with dual-rail source-coupled logic”, IEEE Journal of Solid-State Circuits vol.30, no.11, pp.1239-1245, 1995.

Reena Rani, L.K. Singh and Neelam Sharma, “A Novel design of High Speed Adders Using Quaternary Signed Digit Number System ”International Journal of Computer and Network Security(IJCNS), Vol. 2,No. 9, pp.62-66, September 2010.

A.A.S Awwal, Syed M. Munir, A.T.M. Shafiqul Khalid, Howard E. Michel and O. N. Garcia, “Multivalued Optical Parallel Computation Using An Optical Programmable Logic Array”, Informatica, vol. 24, No. 4, pp. 467-473, 2000.

Vasundara Patel K S, K S Gurumurthy, “Design of High Performance Quaternary Adders”, International Journal of Computer Theory and Engineering, Vol.2, No.6, pp. 944-952, December, 2010.

A.A.S. Awwal and J.U. Ahmed, “fast carry free adder design using QSD number system ,”proceedings of the IEEE 1993 national aerospace and electronic conference, vol 2,pp 1085-1090,1993.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.