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Power Reduction by Flip Flop Merging Technique Using Heuristic Algorithm

V. Nandhini, K. Ramprakash


Power consumed by clocking has taken a major part of the whole design circuit. Given a design, we can reduce its power consumption by replacing several flip-flops with some multi-bit flip-flop. This may affect the performance of the original circuit because of its timing and placement capacity constraints. To overcome this problem efficiently, a technique combination table is built to enumerate possible combinations of flip-flops provided by a library. Finally, merging of flip-flops is done with help of co-ordination transformation and combination table. We can achieve better area reduction and power reduction by 37.65%. The implementation of flip flop merging is done in MODELSIM software and the power analysis through Quartus II.


Clock Power Reduction, Multi-Bit Flip-Flop, Merging, Replacement.

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